Serial Peripheral Interface Bus (SPI) is a digital communication bus commonly used for interconnecting chips on a printed circuit board.

An SPI bus interconnects a master with one or more slaves. Communication is triggered by the master, and is full duplex, i.e. for each byte the master sends to the slave, the slave sends one to the master, at the same time.

An SPI bus consists of the following lines:

• MISO (Master-In-Slave-Out) is used for the slave to send data bits to the master.

• MOSI (Master-Out-Slave-In) is used for the master to send data bits to the slave.

• CLK (clock) is used by the master to output a clock signal to time the transmission of the data bits.

• CS (chip select) or SS (slave select) is used by the master to select which slave it wishes to talk to. There needs to be one independent CS line from the master to each of the slaves.

In a single-master-single-slave scenario, an SPI transaction goes as follows:

• The master lowers the CS line, indicating a transaction is starting

• The master starts outputting a clock signal (a "square wave") on the CLK line

• At each rising edge of the CLK line:

  • The master samples the MISO line. If it's high, that's a 1, if it's low, a 0.

  • The slave samples the MOSI line. If it's high, that's a 1, if it's low, a 0.

• The transaction goes on until the master stops sending a CLK signal, and raises the CS line.

The libraries provided with the 

 allow you to use the SPI in master mode.

The following logic analyzer screen shots illustrate some of the configurations. These were obtained by running the 02-spi project from the 

.

The screenshot below shows the SPI master (the 

 platform) transfering 8 bytes of data (0x0001020304050607)

• There is no slave attached. The MISO line stays high and the master therefore always receives 0xffffffffffffffff.

• The CLK frequency is set to the 1/16th of the CPU clock frequency. With a CPU clock at 7.4MHz, the CLK period is 2.16us.

• Sampling is set up to happen on a rising edge.

• The SS0n pin is used for the CS line.

• Data is sent most-significant-bit (msb) first, i.e. 5 is encoded as b00000101.

Open

The following shows some of the settings of the SPI master module.

Open	Open
the SS0n pin is used as CS line	the SS1n pin is used as CS line

Open	Open
most-significant-bit (msb) first	least-significant-bit (lsb) first

Open	Open
CLK line at 1/16th the CPU speed	CLK line at 1/8th the CPU speed

Open	Open
sampling on the rising edge of CLK	sampling on the falling edge of CLK

Open	Open
CLK is low when not in use	CLK is high when not in use

The 02-spi sample application shows how to use SPI. Compile and load this application on your 

 board.

When you run the application, each second:

• The following bytes are sent over the SPI bus: 0x000102030405060708

• The device prints on the CLI what bytes have been sent and received

  spi app, ver 1.0.0.1 SmartMeshIP stack, ver 1.2.1.3 SPI sent: 00 01 02 03 04 05 06 07 SPI received: 6f 70 71 72 73 74 75 76 SPI sent: 00 01 02 03 04 05 06 07 SPI received: 77 78 79 7a 7b 7c 7d 7e SPI sent: 00 01 02 03 04 05 06 07 SPI received: 7f 80 81 82 83 84 85 86 SPI sent: 00 01 02 03 04 05 06 07 SPI received: 87 88 89 8a 8b 8c 8d 8e SPI sent: 00 01 02 03 04 05 06 07 SPI received: 8f 90 91 92 93 94 95 96